Field of the Invention
The present invention relates generally to a semiconductor device and method of manufacturing a semiconductor device and, more particularly, to a method of manufacturing a semiconductor device which includes planarizing an upper surface of an epitaxial layer.
Description of the Related Art
FIG. 1 illustrates a conventional semiconductor device 100 which includes a silicon substrate 110, a buried oxide layer 120 formed on the substrate 110, a plurality of fin structures 130 (hereinafter “fins”) formed on the buried oxide layer, and a pair of gate electrodes 140 formed on the plurality of fins 130.
The semiconductor device 100 is a field effect transistor (finFET), in which the plurality of fins are formed of a semiconductor (e.g., silicon), a channel region is formed in the center of each of the plurality of fins 130, diffusion regions (e.g., source region, drain region, etc.) 135 are formed in the opposing ends of the fin 130 on either side of the channel region, and the gate electrodes 140 are formed on each side of the fins 130 in an area corresponding to the channel region.
As illustrated in FIG. 1, the plurality of fins (e.g., silicon) have a <110> crystal orientation along the x-axis and along the y-axis.
FIGS. 2A-2C illustrate a conventional method 200 (e.g., a merging process) of merging the diffusion regions (e.g., the source region and drain region) of the plurality of fins 130 in the semiconductor device 100. In particular, FIGS. 2A-2C illustrate a cross-sectional view of a semiconductor device 100 along the x-axis at “II” in FIG. 1, as the semiconductor device 100 is being transformed into a merged source and drain finFET.
The merged source and drain finFET is the device of choice for 14 nm node and beyond. Merging the fins 130 may allow series resistance to be minimized with little, if any, increase in the parasitic capacitance between the gate electrodes 140 and the source/drain regions, and may allow merged source and drain regions to be contacted by a single contact via as well as more flexible placement of the contact via.
As illustrated in FIG. 2A, a merged source and drain finFET is conventionally formed by growing an epitaxial layer 250 (e.g., epitaxial silicon layer) on the source and drain region 135 (e.g., an exposed surface of the source and drain region 135) of the plurality of fins 130.
As illustrated in FIG. 2B, as the epitaxial layer 250 grows on the source and drain regions 135 of the plurality of fins 130, the plurality of fins 130 are merged (e.g., partially or completely merged) by the epitaxial layer 250. Since a top surface of a fin 130 has a <100> crystal orientation, and a sidewall of a fin 130 has a <110> crystal orientation, and since epitaxial growth on different crystal orientations has different growth rates, the epitaxial layer 250 is typically grown as a faceted epitaxial layer 250 with a {111} facet diamond-shape, as illustrated in FIG. 2B.
FIG. 2C illustrates the merged source and drain finFET 290 upon completion of the merging process. As illustrated in FIG. 2C, in the merged source and drain finFET 290, the epitaxial layer 250 includes an upper surface 251 having a peak 251a formed over the plurality of fins 130, and a valley 251b found between the plurality of fins 130 (e.g., formed at a location which is substantially midway between the plurality of fins 130). For example, before the planarizing of the upper surface of the epitaxial layer, a difference between a height of the peak 251a and a height of the valley 251b is typically at least 10 nm.
That is, the conventional method 200 in FIGS. 2A-2C is highly susceptible to forming a non-uniform source and drain height, which results in the surface roughness on the upper surface 251 of the epitaxial layer 250.
The surface roughness of the upper surface 251 of the epitaxial layer 250 causes several concerns. First, the surface roughness may cause a variability in parasitic capacitance in the device 290. Second, the surface roughness may cause the device 290 to be less compatible with a trench silicide module. Third, the surface roughness may facilitate lateral epitaxial growth, especially at a region of an SRAM. Fourth, the surface roughness may facilitate a formation of NiSi2 on the {111} face of the epitaxial layer 250 (e.g., on the upper surface 251), in a subsequent silicidation step.